Processing devices having multiple processor cores often implement a coherency mechanism to maintain coherency between the caches of the different processor cores. These caches often are implemented as unified caches (i.e., configured to store both instruction information and data information). In a typical unified cache, all stored information is kept coherent. As a result, for every cache miss within the processing device, every other target component in the same coherency domain must be queried (or snooped) via a shared interconnect for the identified information. These snoop operations can lead to congestion of the interconnect. The severity of this congestion compounds as more processor cores are utilized. Accordingly, an improved technique for managing coherency in a processing device implementing unified caches would be advantageous.